In high-speed wireless communication techniques for employing pulse communication systems which are typically known as UWB (Ultra Wide-Band), since linearity is not always required, wireless communication apparatuses may be suitably manufactured by utilizing CMOSs (Complementary Metal Oxide Semiconductors), and thus, may be made compact. Also, since RF circuits such as high-precision local signal sources are not required, wireless communication apparatuses are operable under low power consumption. Moreover, since wide bands are utilized, wireless communication apparatuses may realize high-speed communications.
However, although the wireless communication apparatuses have the above-described merits, since data sampling operations for pulse-shaped signals shorter than, or equal to 1 nsec are carried out, synchronous pull-in operations within short times are required and high-precision tracking operations are required, which constitute one of unrealizable problems thereof.
As conventional sample timing generating circuits for generating sample timing that is synchronized with respect to inputted signals, clock data recovery circuits constructed of analog components such as LPFs (Low-Pass Filters) and VCOs (voltage-Controlled Oscillators) have been provided (refer to, for example, patent publication 1).
Also, synchronizing apparatuses have been provided in which inputted signals are over-sampled, sampling timing errors are calculated from these over-sampled data, and phases (timing) of clocks generated by oscillators are adjusted, so that the generated clocks are synchronized with the inputted signal (refer to, for instance, patent publication 2).
FIG. 8 indicates an arrangement of the conventional clock data recovery circuit described in the above-described patent publication 1. Data produced by sampling an input signal “DIN” by a discriminator 1204 is compared with a signal produced by delaying the input signal “DIN” by a delay circuit 1201 by a phase comparator 1212 so as to generate pulses in response to phase errors.
Then, the generated pulses are averaged by an LPF 1206, and a voltage of the averaged pulse is amplified by a GCA (Gain Controlled Amplifier) 1207, and a clock signal having a frequency corresponding to this amplified voltage is generated by a VCO 1203. Since timing of the clock signal is adjusted by a variable phase shifter 1211 based upon the clock signal generated by the VCO 1203 and the timing-adjusted clock signal is supplied to the discriminator 1204, such a clock data recovery circuit capable of obtaining the extracted clock signal that is synchronized with the input signal DIN is arranged.
FIG. 9 indicates an arrangement of the conventional synchronizing apparatus described in the above-described patent publication 2. An input signal “xk” is sampled by an interpolator 1110, the sampled input signal “xk” is PR-equalized by a PR (Partial Response) equalizing unit 1111, and initial sampling timing (phase) is calculated by a ZPR (ZERO PHASE RESTART) 1115. Then, an NCO (Number Controlled Oscillator) 1114 is operated based upon a value obtained by averaging phase errors by an LPF 1113, and a clock produced by the NCO 1114 is applied to the interpolator 1110, so that the synchronizing apparatus capable of synchronizing the clock with the input signal “xk” is arranged. The phase errors are defined between the output of the ZPR 1115 and either the calculated value of the initial sampling timing or the output of the PR equalizing unit 1111 detected by the phase error detector 1112.
However, in the method for using the analog components such as the LPF and the VCO, the time constant becomes long, so that a lengthy time is required in the synchronous pull-in operation. Also, in the method for executing the over sampling process operation, since the synchronizing apparatus is arranged by the interpolator, the NCO (Number Controlled Oscillator), and the like, the arrangement thereof becomes complex. As a consequence, as synchronizing methods that are particularly specialized in pulse communications, the below-mentioned methods have been proposed which may track synchronizations by acquiring correlations among respective signals that have been delayed before and after a reference time (refer to, for instance, patent publication 3).
FIG. 10 is a block diagram for representing an arrangement of a conventional pulse wireless communication apparatus described in the patent publication 3. In FIG. 10, the conventional pulse wireless communication apparatus 1000 has been arranged by an amplifier 1002; a filter 1003; an analog coding unit 1004; splitters 1005 and 1015; a plurality of delaying devices 1006, 1007 and 1008; multipliers 1009, 1010 and 1011; integrators 1012, 1013, and 1014; a reception synchronizing control unit 1017; phase delaying unit 1018; and a main reception wavelet code producing device 1016. The amplifier 1002 amplifies an RF signal received by an antenna 1001. The filter 1003 eliminates an unnecessary signal. The analog coding unit 1004 converts the signal to an analog signal. The splitters 1005 and 1015 split the signals. The delaying devices 1006, 1007, and 1008 delay the signals. The multipliers 1009, 1010, and 1011 multiply the signals. The integrators 1012, 1013, and 1014 integrate times. The reception synchronizing control unit 1017 performs a synchronization judging operation and a delay control operation in response to correlations. The phase delaying unit 1018 delays a phase of a signal. The main reception wavelet code producing device 1016 modulates the phase-delayed signal, and spreads the modulated phase-delayed signal based upon the same spread codes.
With employment of this arrangement, the received RF signal is amplified by the amplifier 1002 so as to become such an RF signal having an amplitude required in a demodulation; an unnecessary frequency band thereof outside the relevant band is eliminated by the filter 1003; and then, an analog code is produced by the analog coding unit 1004. This signal is split by the splitter 1005, and then, 3 pieces of signals delayed by the delaying devices 1006, 1007, and 1008 are outputted. That is, a signal delayed by a time “L”, a signal delayed by a time “L+Y”, and a signal delayed by a time “L−Y” are outputted.
A reference pulse signal produced by the main reception wavelet code producing device 1016 is multiplied with respect to these three signals by the multipliers 1009, 1010, and 1011, respectively. Then, the multiplied pulse signals are integrated by times corresponding to the respective symbols by the integrators 1012, 1013, and 1014. The reception synchronizing control unit 1017 judges synchronizations in response to correlations among the respective signals, and outputs decoded data 1019, while the reception synchronizing control unit 1017 controls the phase delaying unit 1018 so as to perform the sliding synchronization.
At this time, while the reception pulse signal at the time “L” is defined as the reference of the correlation, in such a case that the correlation of the signal of the time “L+Y” becomes higher than that of the signal of the time “L”, the phase delaying unit 1018 delays a tracking time period. Conversely, in such a case that the correlation of the signal of the time “L−Y” becomes higher than that of the signal of the time “L”, since the phase delaying unit 1018 leads the tracking time period, the phases of the time-integrated signals are adjusted in such a manner that these time integrated signals are synchronized with the transmission symbol rate.
Patent Publication 1: JP-A-2006-101268
Patent Publication 2: JP-A-2006-134501
Patent Publication 3: JP-T-2003-535552 (page 148, FIG. 37A)